The 8085 Microprocessor Architecture Programming and Interfacing Paperback 1st Edition by Udaykumar ISBN 8177584553 978-8177584554
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Product details:
ISBN 10:8177584553
ISBN 13:978-8177584554
Author:Udaykumar
The 8085 Microprocessor: Architecture, Programming and Interfacing -Pearson-Udaykumar-2008-EDN-1
Table of contents:
INTRODUCTION
1: Evolution of Microprocessors
1.1 EARLY INTEGRATED CIRCUITS
1.2 4-BIT MICROPROCESSORS
1.3 8-BIT MICROPROCESSORS
1.4 16-BIT MICROPROCESSORS
1.5 32-BIT MICROPROCESSORS
1.6 RECENT MICROPROCESSORS
1.7 MICROCONTROLLERS AND DIGITAL SIGNAL PROCESSORS
2: Fundamentals of a Computer
2.1 CALCULATOR
2.2 COMPUTER
2.3 MICROCOMPUTER
2.4 COMPUTER LANGUAGES
QUESTIONS
3: Number Representation
3.1 UNSIGNED BINARY INTEGERS
3.2 SIGNED BINARY INTEGERS
3.3 REPRESENTATION OF FRACTIONS
3.4 SIGNED FLOATING POINT NUMBERS
QUESTIONS
4: Fundamentals of Microprocessor
4.1 HISTORY OF MICROPROCESSORS
4.2 DESCRIPTION OF 8085 PINS
4.3 PROGRAMMER’S VIEW OF 8085: NEED FOR REGISTERS
4.3.1 MEANING OF PROGRAMMER’S VIEW
4.4 ACCUMULATOR OR REGISTER A
4.5 REGISTERS B, C, D, E, H, AND L
QUESTIONS
5: First Assembly Language Program
5.1 PROBLEM STATEMENT
5.2 ABOUT THE MICROPROCESSOR KIT
5.3 USING THE MICROPROCESSOR KIT IN SERIAL MODE
QUESTIONS
6: Data Transfer Group of Instructions
6.1 CLASSIFICATION OF 8085 INSTRUCTIONS
6.2 INSTRUCTION TYPE MVI r, d8
6.3 INSTRUCTION TYPE MOV r1, r2
6.4 INSTRUCTION TYPE MOV r, M
6.5 INSTRUCTION TYPE MOV M, r
6.6 INSTRUCTION TYPE LXI rp, d16
6.7 INSTRUCTION TYPE MVI M, d8
6.8 INSTRUCTION TYPE LDA a16
6.9 INSTRUCTION TYPE STA a16
6.10 INSTRUCTION TYPE XCHG
6.11 ADDRESSING MODES OF 8085
6.12 INSTRUCTION TYPE LDAX rp
6.13 INSTRUCTION TYPE STAX rp
6.14 INSTRUCTION TYPE LHLD a16
6.15 INSTRUCTION TYPE SHLD a16
QUESTIONS
7: Arithmetic Group of Instructions
7.1 INSTRUCTIONS TO PERFORM ADDITION
7.2 INSTRUCTIONS TO PERFORM SUBTRACTION
7.3 INSTRUCTION TYPE INX rp
7.4 INSTRUCTION TYPE DCX rp
7.5 INSTRUCTION TYPE DAD rp
7.6 DECIMAL ADDITION IN 8085
QUESTIONS
8: Logical Group of Instructions
8.1 INSTRUCTIONS TO PERFORM ‘AND’ OPERATION
8.2 INSTRUCTIONS TO PERFORM ‘OR’ OPERATION
8.3 INSTRUCTIONS TO PERFORM ‘EXCLUSIVE OR’ OPERATION
8.4 INSTRUCTION TO COMPLEMENT ACCUMULATOR
8.5 INSTRUCTIONS TO COMPLEMENT/SET ‘Cy’ FLAG
8.6 INSTRUCTIONS TO PERFORM COMPARE OPERATION
8.7 INSTRUCTIONS TO ROTATE ACCUMULATOR
QUESTIONS
9: NOP and Stack Group of Instructions
9.1 STACK AND THE STACK POINTER
9.2 INSTRUCTION TYPE POP rp
9.3 INSTRUCTION TYPE PUSH rp
9.4 INSTRUCTION TYPE LXI SP, d16
9.5 INSTRUCTION TYPE SPHL
9.6 INSTRUCTION TYPE XTHL
9.7 INSTRUCTION TYPE INX SP
9.8 INSTRUCTION TYPE DCX SP
9.9 INSTRUCTION TYPE DAD SP
9.10 INSTRUCTION TYPE NOP
QUESTIONS
10: Branch Group of Instructions
10.1 MORE DETAILS ABOUT PROGRAM EXECUTION
10.2 UNCONDITIONAL JUMP INSTRUCTIONS
10.3 CONDITIONAL JUMP INSTRUCTIONS
10.4 UNCONDITIONAL CALL AND RETURN INSTRUCTIONS
10.5 CONDITIONAL CALL INSTRUCTIONS
10.6 CONDITIONAL RETURN INSTRUCTIONS
10.7 RST n —RESTART INSTRUCTIONS
QUESTIONS
11: Chip Select Logic
11.1 CONCEPT OF CHIP SELECTION
11.2 RAM CHIP PIN DETAILS AND ADDRESS RANGE
11.3 MULTIPLE MEMORY ADDRESS RANGE
11.4 WORKING OF 74138 DECODER IC
11. USE OF 74138 TO GENERATE CHIP SELECT LOGIC
11.6 USE OF 74138 IN ALS-SDA-85M KIT
QUESTIONS
12: Addressing of I/O Ports
12.1 NEED FOR I/O PORTS
12.2 IN AND OUT INSTRUCTIONS
12.3 MEMORY-MAPPED I/O
12.4 I/O-MAPPED I/O
12.5 COMPARISON OF MEMORY-MAPPED I/O AND I/O-MAPPED I/O
QUESTIONS
13: Architecture of 8085
13.1 DETAILS OF 8085 ARCHITECTURE
13.2 INSTRUCTION CYCLE
13.3 COMPARISON OF DIFFERENT MACHINE CYCLES
13.4 MEMORY SPEED REQUIREMENT
13.5 WAIT STATE GENERATION
QUESTIONS
II: Assembly Language Programs
INTRODUCTION
14: Simple Assembly Language Programs
14.1 EXCHANGE 10 BYTES
14.2 ADD TWO MULTI-BYTE NUMBERS
14.3 ADD TWO MULTI-BYTE BCD NUMBERS
14.4 BLOCK MOVEMENT WITHOUT OVERLAP
14.5 BLOCK MOVEMENT WITH OVERLAP
14.6 ADD N NUMBERS OF SIZE 8 BITS
14.7 CHECK THE FOURTH BIT OF A BYTE
14.8 SUBTRACT TWO MULTI-BYTE NUMBERS
14.9 MULTIPLY TWO NUMBERS OF SIZE 8 BITS
14.10 DIVIDE A 16-BIT NUMBER BY AN 8-BIT NUMBER
QUESTIONS
15: Use of PC in Writing and Executing 8085 Programs
15.1 STEPS NEEDED TO RUN AN ASSEMBLY LANGUAGE PROGRAM
15.2 CREATION OF .ASM FILE USING A TEXT EDITOR
15.3 GENERATION OF .OBJ FILE USING A CROSS-ASSEMBLER
15.4 GENERATION OF .HEX FILE USING A LINKER
15.5 DOWNLOADING THE MACHINE CODE TO THE KIT
15.6 RUNNING THE DOWNLOADED PROGRAM ON THE KIT
15.7 RUNNING THE PROGRAM USING THE PC AS A TERMINAL
QUESTIONS
16: Aditional Assembly Language Programs
16.1 SEARCH FOR A NUMBER USING LINEAR SEARCH
16.2 FIND THE SMALLEST NUMBER
16.3 COMPUTE THE HCF OF TWO 8-BIT NUMBERS
16.4 CHECK FOR ‘2 OUT OF 5’ CODE
16.5 CONVERT ASCII TO BINARY
16.6 CONVERT BINARY TO ASCII
16.7 CONVERT BCD TO BINARY
16.8 CONVERT BINARY TO BCD
16.9 CHECK FOR PALINDROME
16.10 COMPUTE THE LCM OF TWO 8-BIT NUMBERS
16.11 SORT NUMBERS USING BUBBLE SORT
16.12 SORT NUMBERS USING SELECTION SORT
16.13 SIMULATE DECIMAL UP COUNTER
16.14 SIMULATE DECIMAL DOWN COUNTER
16.15 DISPLAY ALTERNATELY 00 AND FF IN THE DATA FIELD
16.16 SIMULATE A REAL-TIME CLOCK
QUESTIONS
17: More Complex Assembly Language Programs
17.1 SUBTRACT MULTI-BYTE BCD NUMBERS
17.2 CONVERT 16-BIT BINARY TO BCD
17.3 DO AN OPERATION ON TWO NUMBERS BASED ON THE VALUE OF X
17.4 DO AN OPERATION ON TWO BCD NUMBERS BASED ON THE VALUE OF X
17.5 BUBBLE SORT IN ASCENDING/DESCENDING ORDER AS PER CHOICE
17.6 SELECTION SORT IN ASCENDING/DESCENDING ORDER AS PER CHOICE
17.7 ADD CONTENTS OF N WORD LOCATIONS
17.8 MULTIPLY TWO 8-BIT NUMBERS (SHIFT AND ADD METHOD)
17.9 MULTIPLY TWO 2-DIGIT BCD NUMBERS
17.10 MULTIPLY TWO 16-BIT BINARY NUMBERS
QUESTIONS
III: Programmable and Non-Programmable I/O Ports
INTRODUCTION
18: Interrupts in 8085
18.1 DATA TRANSFER SCHEMES
18.2 GENERAL DISCUSSION ABOUT 8085 INTERRUPTS
18.3 EI AND DI INSTRUCTIONS
18.4 INTR AND INTA* PINS
18.5 RST5.5 AND RST6.5 PINS
18.6 RST7.5 PIN
18.7 TRAP INTERRUPT PIN
18.8 EXECUTION OF ‘DAD rp’ INSTRUCTION
18.9 SIM AND RIM INSTRUCTIONS
18.10 HLT INSTRUCTION
18.11 PROGRAMS USING INTERRUPTS
QUESTIONS
19: 8212 Non-Programmable 8-Bit I/O Port
19.1 WORKING OF 8212
19.2 APPLICATIONS OF 8212
QUESTIONS
20: 8255 Programmable Peripheral Interface Chip
20.1 DESCRIPTION OF 8255 PPI
20.2 OPERATIONAL MODES OF 8255
20.3 CONTROL PORT OF 8255
20.4 MODE 1—STROBED I/O
20.5 MODE 2—BI-DIRECTIONAL I/O
QUESTIONS
21: Programs using Interface Modules
21.1 DESCRIPTION OF LOGIC CONTROLLER INTERFACE
21.2 SUCCESSIVE APPROXIMATION ADC INTERFACE
21.3 DUAL SLOPE ADC INTERFACE
21.4 DIGITAL TO ANALOG CONVERTER INTERFACE
21.5 STEPPER MOTOR INTERFACE
QUESTIONS
IV: Support Chips
INTRODUCTION
22: Interfacing of I/o Devices
22.1 INTERFACING 7-SEGMENT DISPLAY
22.2 DISPLAY INTERFACE USING SERIAL TRANSFER
22..3 INTERFACING A SIMPLE KEYBOARD
22.4 INTERFACING A MATRIX KEYBOARD
22..5 DESCRIPTION OF MATRIX KEYBOARD INTERFACE
22.6 INTEL 8279 KEYBOARD AND DISPLAY CONTROLLER
22.7 PROGRAMS USING 8279
QUESTIONS
23: Intel 8259A— Programmable Interrupt Controller
23.1 NEED FOR AN INTERRUPT CONTROLLER
23.2 OVERVIEW OF THE WORKING OF 8259
23.3 PINS OF 8259
23.4 REGISTERS USED IN 8259
23.5 PROGRAMMING THE 8259 WITH NO SLAVES
23.6 PROGRAMMING THE 8259 WITH SLAVES
23.7 USE OF 8259 IN AN 8086-BASED SYSTEM
23.8 ARCHITECTURE OF 8259
QUESTIONS
24: Intel 8257—Programmable DMA Controller
24.1 CONCEPT OF DIRECT MEMORY ACCESS (DMA)
24.2 NEED FOR DMA DATA TRANSFER
24.3 DESCRIPTION OF 8257 DMA CONTROLLER CHIP
24.4 PROGRAMMING THE 8257
24.5 DESCRIPTION OF THE PINS OF 8257
24.6 WORKING OF THE 8257 DMA CONTROLLER
24.7 STATE DIAGRAM OF 8085
QUESTIONS
25: Intel 8253—Programmable Interval Timer
25.1 NEED FOR PROGRAMMABLE INTERVAL TIMER
25.2 DESCRIPTION OF 8253 TIMER
25.3 PROGRAMMING THE 8253
25.4 MODE 0—INTERRUPT ON TERMINAL COUNT
25.5 MODE 1—RE-TRIGGERABLE MONO-STABLE MULTI
25.6 MODE 2—RATE GENERATOR
25.7 MODE 3—SQUARE WAVE GENERATOR
25.8 MODE 4—SOFTWARE-TRIGGERED STROBE
25.9 MODE 5—HARDWARE-TRIGGERED STROBE
25.10 USE OF 8253 IN ALS-SDA-85 KIT
QUESTIONS
26: Intel 8251A—Universal Synchronous Asynchronous Receiver Transmitter (USART)
26.1 NEED FOR USART
26.2 ASYNCHRONOUS TRANSMISSION
26.3 ASYNCHRONOUS RECEPTION
26.4 SYNCHRONOUS TRANSMISSION
26.5 SYNCHRONOUS RECEPTION
26.6 PIN DESCRIPTION OF 8251 USART
26.7 PROGRAMMING THE 8251
26.8 USE OF SOD PIN OF 8085 FOR SERIAL TRANSFER
QUESTIONS
27: Zilog Z-80 Microprocessor
27.1 COMPARISON OF INTEL 8080 WITH INTEL 8085
27.2 PROGRAMMER’S VIEW OF Z-80
27.3 SPECIAL FEATURES OF Z-80
27.4 ADDRESSING MODES OF Z-80
27.5 SPECIAL INSTRUCTION TYPES
27.6 PINS OF Z-80
27.7 INTERRUPT STRUCTURE IN Z-80
27.8 PROGRAMMING EXAMPLES
27.9 INSTRUCTION SET SUMMARY
QUESTIONS
28: Motorola M6800 Microprocessor
28.1 PIN DESCRIPTION OF 6800
28.2 PROGRAMMER’s VIEW OF 6800
28.3 ADDRESSING MODES OF 6800
28.4 INSTRUCTION SET OF 6800
28.5 INTERRUPTS OF 6800
PROGRAMMING EXAMPLES
QUESTIONS
29: 8051 Microcontroller
29.1 MAIN FEATURES OF INTEL 8051
29.2 FUNCTIONAL BLOCKS OF INTEL 8051
29.3 PROGRAM MEMORY STRUCTURE
29.4 DATA MEMORY STRUCTURE
29.5 PROGRAMMER’S VIEW OF 8051
29.6 ADDRESSING MODES OF 8051
29.7 INSTRUCTION SET OF 8051
29.8 PROGRAMMING EXAMPLES
QUESTIONS
30: Advanced Topics In 8051
30.1 INTERRUPT STRUCTURE OF 8051
30.2 TIMERS OF 8051
30.3 SERIAL INTERFACE
30.4 STRUCTURE AND OPERATION OF PORTS
30.5 POWER SAVING MODES OF 8051
30.6 PROGRAMMING OF EPROM IN 8751BH
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Udaykuma,Microprocessor,Architecture