Multi Core Embedded Systems 1st Edition by Georgios Kornaros ISBN 1351834088 9781351834087

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ISBN 10: 1351834088 
ISBN 13: 9781351834087
Author: Georgios Kornaros

Details a real-world product that applies a cutting-edge multi-core architecture Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner. Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth. Discusses the available programming models spread across different abstraction levels The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as: Architectures and interconnects Embedded design methodologies Mapping of applications.

Multi Core Embedded Systems 1st Table of contents:

1 Multi-Core Architectures for Embedded Systems
1.1 Introduction
1.1.1 What Makes Multiprocessor Solutions Attractive?
1.2 Architectural Considerations
1.3 Interconnection Networks
1.4 Software Optimizations
1.5 Case Studies
1.5.1 HiBRID-SoC for Multimedia Signal Processing
1.5.2 VIPER Multiprocessor SoC
1.5.3 Defect-Tolerant and Reconfigurable MPSoC
1.5.4 Homogeneous Multiprocessor for Embedded Printer Application
1.5.5 General Purpose Multiprocessor DSP
1.5.6 Multiprocessor DSP for Mobile Applications
1.5.7 Multi-Core DSP Platforms
1.6 Conclusions
Review Questions
Bibliography
2 Application-Specific Customizable Embedded Systems
2.1 Introduction
2.2 Challenges and Opportunities
2.2.1 Objectives
2.3 Categorization
2.3.1 Customized Application-Specific Processor Techniques
2.3.2 Customized Application-Specific On-Chip Interconnect Techniques
2.4 Configurable Processors and Instruction Set Synthesis
2.4.1 Design Methodology for Processor Customization
2.4.2 Instruction Set Extension Techniques
2.4.3 Application-Specific Memory-Aware Customization
2.4.4 Customizing On-Chip Communication Interconnect
2.4.5 Customization of MPSoCs
2.5 Reconfigurable Instruction Set Processors
2.5.1 Warp Processing
2.6 Hardware/Software Codesign
2.7 Hardware Architecture Description Languages
2.7.1 LISATek Design Platform
2.8 Myths and Realities
2.9 Case Study: Realizing Customizable Multi-Core Designs
2.10 The Future: System Design with Customizable Architectures, Software, and Tools
Review Questions
Bibliography
3 Power Optimization in Multi-Core System-on-Chip
3.1 Introduction
3.2 Low Power Design
3.2.1 Power Models
3.2.2 Power Analysis Tools
3.3 PKtool
3.3.1 Basic Features
3.3.2 Power Models
3.3.3 Augmented Signals
3.3.4 Power States
3.3.5 Application Examples
3.4 On-Chip Communication Architectures
3.5 NOCEXplore
3.5.1 Analysis
3.6 DPM and DVS in Multi-Core Systems
3.7 Conclusions
Review Questions
Bibliography
4 Routing Algorithms for Irregular Mesh-Based Network-on-Chip
4.1 Introduction
4.2 An Overview of Irregular Mesh Topology
4.2.1 2D Mesh Topology
4.2.2 Irregular Mesh Topology
4.3 Fault-Tolerant Routing Algorithms for 2D Meshes
4.3.1 Fault-Tolerant Routing Using Virtual Channels
4.3.2 Fault-Tolerant Routing with Turn Model
4.4 Routing Algorithms for Irregular Mesh Topology
4.4.1 Traffic-Balanced OAPR Routing Algorithm
4.4.2 Application-Specific Routing Algorithm
4.5 Placement for Irregular Mesh Topology
4.5.1 OIP Placements Based on Chen and Chiu’s Algorithm
4.5.2 OIP Placements Based on OAPR
4.6 Hardware Efficient Routing Algorithms
4.6.1 Turns-Table Routing (TT)
4.6.2 XY-Deviation Table Routing (XYDT)
4.6.3 Source Routing for Deviation Points (SRDP)
4.6.4 Degree Priority Routing Algorithm
4.7 Conclusions
Review Questions
Bibliography
5 Debugging Multi-Core Systems-on-Chip
5.1 Introduction
5.2 Why Debugging Is Difficult
5.2.1 Limited Internal Observability
5.2.2 Asynchronicity and Consistent Global States
5.2.3 Non-Determinism and Multiple Traces
5.3 Debugging an SoC
5.3.1 Errors
5.3.2 Example Erroneous System
5.3.3 Debug Process
5.4 Debug Methods
5.4.1 Properties
5.4.2 Comparing Existing Debug Methods
5.5 CSAR Debug Approach
5.5.1 Communication-Centric Debug
5.5.2 Scan-Based Debug
5.5.3 Run/Stop-Based Debug
5.5.4 Abstraction-Based Debug
5.6 On-Chip Debug Infrastructure
5.6.1 Overview
5.6.2 Monitors
5.6.3 Computation-Specific Instrument
5.6.4 Protocol-Specific Instrument
5.6.5 Event Distribution Interconnect
5.6.6 Debug Control Interconnect
5.6.7 Debug Data Interconnect
5.7 Off-Chip Debug Infrastructure
5.7.1 Overview
5.7.2 Abstractions Used by Debugger Software
5.8 Debug Example
5.9 Conclusions
Review Questions
Bibliography
6 System-Level Tools for NoC-Based Multi-Core Design
6.1 Introduction
6.1.1 Related Work
6.2 Synthetic Traffic Models
6.3 Graph Theoretical Analysis
6.3.1 Generating Synthetic Graphs Using TGFF
6.4 Task Mapping for SoC Applications
6.4.1 Application Task Embedding and Quality Metrics
6.4.2 SCOTCH Partitioning Tool
6.5 OMNeT++ Simulation Framework
6.6 A Case Study
6.6.1 Application Task Graphs
6.6.2 Prospective NoC Topology Models
6.6.3 Spidergon Network on Chip
6.6.4 Task Graph Embedding and Analysis
6.6.5 Simulation Models for Proposed NoC Topologies
6.6.6 Mpeg4: A Realistic Scenario
6.7 Conclusions and Extensions
Review Questions
Bibliography
7 Compiler Techniques for Application Level Memory Optimization for MPSoC
7.1 Introduction
7.2 Loop Transformation for Single and Multiprocessors
7.3 Program Transformation Concepts
7.4 Memory Optimization Techniques
7.4.1 Loop Fusion
7.4.2 Tiling
7.4.3 Buffer Allocation
7.5 MPSoC Memory Optimization Techniques
7.5.1 Loop Fusion
7.5.2 Comparison of Lexicographically Positive and Positive Dependency
7.5.3 Tiling
7.5.4 Buffer Allocation
7.6 Technique Impacts
7.6.1 Computation Time
7.6.2 Code Size Increase
7.7 Improvement in Optimization Techniques
7.7.1 Parallel Processing Area and Partitioning
7.7.2 Modulo Operator Elimination
7.7.3 Unimodular Transformation
7.8 Case Study
7.8.1 Cache Ratio and Memory Space
7.8.2 Processing Time and Code Size
7.9 Discussion
7.10 Conclusions
Review Questions
Bibliography
8 Programming Models for Multi-Core Embedded Software
8.1 Introduction
8.2 Thread Libraries for Multi-Threaded Programming
8.3 Protections for Data Integrity in a Multi-Threaded Environment
8.3.1 Mutual Exclusion Primitives for Deterministic Output
8.3.2 Transactional Memory
8.4 Programming Models for Shared Memory and Distributed Memory
8.4.1 OpenMP
8.4.2 Thread Building Blocks
8.4.3 Message Passing Interface
8.5 Parallel Programming on Multiprocessors
8.6 Parallel Programming Using Graphic Processors
8.7 Model-Driven Code Generation for Multi-Core Systems
8.7.1 StreamIt
8.8 Synchronous Programming Languages
8.9 Imperative Synchronous Language: Esterel
8.9.1 Basic Concepts
8.9.2 Multi-Core Implementations and Their Compilation Schemes
8.10 Declarative Synchronous Language: LUSTRE
8.10.1 Basic Concepts
8.10.2 Multi-Core Implementations from LUSTRE Specifications
8.11 Multi-Rate Synchronous Language: SIGNAL
8.11.1 Basic Concepts
8.11.2 Characterization and Compilation of SIGNAL
8.11.3 SIGNAL Implementations on Distributed Systems
8.11.4 Multi-Threaded Programming Models for SIGNAL
8.12 Programming Models for Real-Time Software
8.12.1 Real-Time Extensions to Synchronous Languages
8.13 Future Directions for Multi-Core Programming
Review Questions
Bibliography
9 Operating System Support for Multi-Core Systems-on-Chips
9.1 Introduction
9.2 Ideal Software Organization
9.3 Programming Challenges
9.4 General Approach
9.4.1 Board Support Package
9.4.2 General Purpose Operating System
9.5 Real-Time and Component-Based Operating System Models
9.5.1 Automated Application Code Generation and RTOS Modeling
9.5.2 Component-Based Operating System
9.6 Pros and Cons
9.7 Conclusions
Review Questions
Bibliography
10 Autonomous Power Management in Embedded Multi-Cores
10.1 Introduction
10.1.1 Why Is Autonomous Power Management Necessary?
10.2 Survey of Autonomous Power Management Techniques
10.2.1 Clock Gating
10.2.2 Power Gating
10.2.3 Dynamic Voltage and Frequency Scaling
10.2.4 Smart Caching
10.2.5 Scheduling
10.2.6 Commercial Power Management Tools
10.3 Power Management and RTOS
10.4 Power-Smart RTOS and Processor Simulators
10.4.1 Chip Multi-Threading (CMT) Architecture Simulator
10.5 Autonomous Power Saving in Multi-Core Processors
10.5.1 Opportunities to Save Power
10.5.2 Strategies to Save Power
10.5.3 Case Study: Power Saving in Intel Centrino
10.6 Power Saving Algorithms
10.6.1 Local PMU Algorithm
10.6.2 Global PMU Algorithm
10.7 Conclusions
Review Questions
Bibliography
11 Multi-Core System-on-Chip in Real World Products
11.1 Introduction
11.2 Overview of picoArray Architecture
11.2.1 Basic Processor Architecture
11.2.2 Communications Interconnect
11.2.3 Peripherals and Hardware Functional Accelerators
11.3 Tool Flow
11.3.1 picoVhdl Parser (Analyzer, Elaborator, Assembler)
11.3.2 C Compiler
11.3.3 Design Simulation
11.3.4 Design Partitioning for Multiple Devices
11.3.5 Place and Switch
11.3.6 Debugging
11.4 picoArray Debug and Analysis
11.4.1 Language Features
11.4.2 Static Analysis
11.4.3 Design Browser
11.4.4 Scripting
11.4.5 Probes
11.4.6 FileIO
11.5 Hardening Process in Practice
11.5.1 Viterbi Decoder Hardening
11.6 Design Example
11.7 Conclusions
Review Questions
Bibliography
12 Embedded Multi-Core Processing for Networking
12.1 Introduction
12.2 Overview of Proposed NPU Architectures
12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks
12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs
12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching
12.3 Programmable Packet Processing Engines
12.3.1 Parallelism
12.3.2 Multi-Threading Support
12.3.3 Specialized Instruction Set Architectures
12.4 Address Lookup and Packet Classification Engines
12.4.1 Classification Techniques
12.4.2 Case Studies
12.5 Packet Buffering and Queue Management Engines
12.5.1 Performance Issues
12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware
12.6 Scheduling Engines
12.6.1 Data Structures in Scheduling Architectures
12.6.2 Task Scheduling
12.6.3 Traffic Scheduling
12.7 Conclusions

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