Sale!

Computer Principles and Design in Verilog HDL 1st Edition by Yamin Li ISBN 1118841093 9781118841099

Original price was: $50.00.Current price is: $35.00.

Computer Principles and Design in Verilog HDL 1st Edition Yamin Li Digital Instant Download

Author(s): Yamin Li
ISBN(s): 9781118841099, 1118841093
Edition: 1
File Details: PDF, 20.64 MB
Year: 2015
Language: english
SKU: EB-5403430 Category: Tag:

Computer Principles and Design in Verilog HDL 1st Edition by Yamin Li – Ebook PDF Instant Download/Delivery: 1118841093, 9781118841099
Full download Computer Principles and Design in Verilog HDL 1st Edition after payment

Product details:

ISBN 10: 1118841093 
ISBN 13: 9781118841099
Author: Yamin Li

Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills

• Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design
• Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation
• Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques
• A companion website includes color figures, Verilog HDL codes, extra test benches not found in the book, and PDFs of the figures and simulation waveforms for instructors

Computer Principles and Design in Verilog HDL 1st Table of contents:

Chapter 1: Computer Fundamentals and Performance Evaluation
1.1 Overview of Computer Systems
1.2 Basic Structure of Computers
1.3 Improving Computer Performance
1.4 Hardware Description Languages
Exercises

Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL
2.1 Logic Gates
2.2 Logic Circuit Design in Verilog HDL
2.3 CMOS Logic Gates
2.4 Four Levels/Styles of Verilog HDL
2.5 Combinational Circuit Design
2.6 Sequential Circuit Design
Exercises

Chapter 3: Computer Arithmetic Algorithms and Implementations
3.1 Binary Integers
3.2 Binary Addition and Subtraction
3.3 Binary Multiplication Algorithms
3.4 Binary Division Algorithms
3.5 Binary Square Root Algorithms
Exercises

Chapter 4: Instruction Set Architecture and ALU Design
4.1 Instruction Set Architecture
4.2 MIPS Instruction Format and Registers
4.3 MIPS Instructions and AsmSim Tool
4.4 ALU Design
Exercises

Chapter 5: Single-Cycle CPU Design in Verilog HDL
5.1 The Circuits Required for Executing an Instruction
5.2 Register File Design
5.3 Single-Cycle CPU Datapath Design
5.4 Single-Cycle CPU Control Unit Design
5.5 Test Program and Simulation Waveform
Exercises

Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL
6.1 Exceptions and Interrupts
6.2 Design of CPU with Exception and Interrupt Mechanism
6.3 The CPU Exception and Interrupt Tests
Exercises

Chapter 7: Multiple-Cycle CPU Design in Verilog HDL
7.1 Dividing Instruction Execution into Several Clock Cycles
7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes
7.3 Multiple-Cycle CPU Control Unit Design
7.4 Memory and Test Program
Exercises

Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL
8.1 Pipelining
8.2 Pipeline Hazards and Solutions
8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes
8.4 Precise Interrupts/Exceptions in Pipelined CPU
8.5 Design of Pipelined CPU with Precise Interrupt/Exception
Exercises

Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL
9.1 IEEE 754 Floating-Point Data Formats
9.2 Converting between Floating-Point Number and Integer
9.3 Floating-Point Adder (FADD) Design
9.4 Floating-Point Multiplier (FMUL) Design
9.5 Floating-Point Divider (FDIV) Design
9.6 Floating-Point Square Root (FSQRT) Design
Exercises

Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL
10.1 CPU/FPU Pipeline Model
10.2 Design of Register File with Two Write Ports
10.3 Data Dependency and Pipeline Stalls
10.4 Pipelined CPU/FPU Design in Verilog HDL
10.5 Memory Modules and Pipelined CPU/FPU Test
Exercises

Chapter 11: Memory Hierarchy and Virtual Memory Management
11.1 Memory
11.2 Cache Memory
11.3 Virtual Memory Management and TLB Design
11.4 Mechanism of TLB-Based MIPS Memory Management
Exercises

Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL
12.1 Overall Structure of Caches and TLBs
12.2 Design of Circuits Related to Caches
12.3 Design of Circuits Related to TLB
12.4 Design of CPU with Caches and TLBs
12.5 Simulation Waveforms of CPU with Caches and TLBs
Exercises

Chapter 13: Multithreading CPU and Multicore CPU Design in Verilog HDL
13.1 Overview of Multithreading CPUs
13.2 Multithreading CPU Design
13.3 Overview of Multicore CPUs
13.4 Multicore CPU Design
Exercises

Chapter 14: Input/Output Interface Controller Design in Verilog HDL
14.1 Overview of Input/Output Interface Controllers
14.2 Error Detection and Correction
14.3 Universal Asynchronous Receiver Transmitter
14.4 PS/2 Keyboard/Mouse Interface Design
14.5 Video Graphics Array (VGA) Interface Design
14.6 Input/Output Buses
Exercises

Chapter 15: High-Performance Computers and Interconnection Networks
15.1 Category of High-Performance Computers
15.2 Shared-Memory Parallel Multiprocessor Systems
15.3 Inside of Interconnection Networks
15.4 Topological Properties of Interconnection Networks
15.5 Some Popular Topologies of Interconnection Networks
15.6 Collective Communications
15.7 Low-Node-Degree Short-Diameter Interconnection Networks

People also search for Computer Principles and Design in Verilog HDL 1st:

    
computer principles and design in verilog hdl pdf
    
principles of verilog digital design pdf
    
8 principles of hci
    
8 bit processor verilog
    
7 principles of digital design

Tags: Yamin Li, Computer Principles, Design, Verilog HDL