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Microprocessor Architecture From Simple Pipelines to Chip Multiprocessors 1st Edition by Jean Loup Baer ISBN 0521769922 9780521769921

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Microprocessor Architecture From Simple Pipelines to Chip Multiprocessors 1st Edition Jean-Loup Baer Digital Instant Download

Author(s): Jean-Loup Baer
ISBN(s): 9780521769921, 0521769922
Edition: 1
File Details: PDF, 1.66 MB
Year: 2009
Language: english
SKU: EB-1378030 Category: Tag:

Microprocessor Architecture From Simple Pipelines to Chip Multiprocessors 1st Edition by Jean Loup Baer – Ebook PDF Instant Download/Delivery: 0521769922, 9780521769921
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ISBN 10: 0521769922
ISBN 13: 9780521769921
Author: Jean Loup Baer

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

Microprocessor Architecture From Simple Pipelines to Chip Multiprocessors 1st Table of contents:

1 Introduction
1.1 A Quick View of Technological Advances
1.2 Performance Metrics
1.3 Performance Evaluation
1.4 Summary
1.5 Further Reading and Bibliographical Notes
EXERCISES
REFERENCES

2 The Basics
2.1 Pipelining
2.2 Caches
2.3 Virtual Memory and Paging
2.4 Summary
2.5 Further Reading and Bibliographical Notes
EXERCISES
REFERENCES

3 Superscalar Processors
3.1 From Scalar to Superscalar Processors
3.2 Overview of the Instruction Pipeline of the DEC Alpha 21164
3.3 Introducing Register Renaming, Reorder Buffer, and Reservation Stations
3.4 Overview of the Pentium P6 Microarchitecture
3.5 VLIW/EPIC Processors
3.6 Summary
3.7 Further Reading and Bibliographical Notes
EXERCISES
REFERENCES

4 Front-End: Branch Prediction, Instruction Fetching, and Register Renaming
4.1 Branch Prediction
Sidebar: The DEC Alpha 21264 Branch Predictor
4.2 Instruction Fetching
4.3 Decoding
4.4 Register Renaming (a Second Look)
4.5 Summary
4.6 Further Reading and Bibliographical Notes
EXERCISES
Programming Projects
REFERENCES

5 Back-End: Instruction Scheduling, Memory Access Instructions, and Clusters
5.1 Instruction Issue and Scheduling (Wakeup and Select)
5.2 Memory-Accessing Instructions
5.3 Back-End Optimizations
5.4 Summary
5.5 Further Reading and Bibliographical Notes
EXERCISES
Programming Project
REFERENCES

6 The Cache Hierarchy
6.1 Improving Access to L1 Caches
6.2 Hiding Memory Latencies
6.3 Design Issues for Large Higher-Level Caches
6.4 Main Memory
6.5 Summary
6.6 Further Reading and Bibliographical Notes
EXERCISES
Programming Projects
REFERENCES

7 Multiprocessors
7.1 Multiprocessor Organization
7.2 Cache Coherence
7.3 Synchronization
7.4 Relaxed Memory Models
7.5 Multimedia Instruction Set Extensions
7.6 Summary
7.7 Further Reading and Bibliographical Notes
EXERCISES
REFERENCES

8 Multithreading and (Chip) Multiprocessing
8.1 Single-Processor Multithreading
8.2 General-Purpose Multithreaded Chip Multiprocessors
8.3 Special-Purpose Multithreaded Chip Multiprocessors
8.4 Summary
8.5 Further Reading and Bibliographical Notes
EXERCISES
REFERENCES

9 Current Limitations and Future Challenges
9.1 Power and Thermal Management
9.2 Technological Limitations: Wire Delays and Pipeline Depths
9.3 Challenges for Chip Multiprocessors
9.4 Summary
9.5 Further Reading and Bibliographical Notes

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Tags: Jean Loup Baer, Microprocessor, Chip Multiprocessors